Recently, semiconductor devices such as a LSI or the like have been required to have higher density in order to meet requirements for reducing the mounting space or for improving the processing rate. As an example of a technology that achieves the high density, there has been known a multilayer wiring technology of manufacturing a multilayer substrate, such as a three-dimensional LSI or the like, by stacking multiple wiring substrates.
According to the multilayer wiring technology, a silicon substrate is prepared, and an adhesion layer is formed on a recess of the silicon substrate or an insulating film, a silicon film and the like formed on the silicon substrate (substrate). A catalyst layer is formed on the adhesion layer, and copper (Cu), which is used as a conductive material, is buried in the recess. In this case, a Cu diffusion barrier film needs to be formed within the recess, and a seed film needs to be formed on the Cu diffusion barrier film by an electroless Cu plating method. Accordingly, a wiring volume of a wiring layer may be reduced or a void may be formed in the buried Cu. Meanwhile, there has been also proposed a method of burying, instead of Cu, a nickel (Ni)-based metal in the recess of the substrate by an electroless plating method and using the Ni-based metal as the wiring layer (electroless Ni plating layer).
The electroless Ni plating layer formed on the silicon substrate or on the insulating film, the silicon film and the like of the silicon substrate with the adhesion layer and the catalyst layer therebetween is silicided by being combined with silicon of the silicon substrate.
In this case, however, if the adhesion layer on the silicon substrate or on the insulating film, the silicon film and the like formed on the silicon substrate has an excessively large thickness, the silicidation of the Ni plating layer may not occur.
Patent Document 1: Japanese Patent Laid-open Publication No. 2010-184113